1. Field of the Invention
The invention relates to a circuit for reproducing bit timing, and more particularly to such a circuit for detecting a timing gap between a sampling clock and an optimal sampling clock, based on a real part digital signal and an imaginary part digital signal obtained by digitizing a real part and an imaginary part of a complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase.
2. Description of the Related Art
An apparatus for demodulating burst signals having been modulated into a digital phase is often provided at an input stage thereof with an automatic gain control circuit (hereinafter, referred to simply as xe2x80x9cAGCxe2x80x9d) in order to suppress fluctuation in received signals in a transmission path. It is necessary to use a preamble in order to converge AGC.
As is well known, a preamble is a signal indicating that data to be transmitted from a transmitter to a receiver at any time has been transmitted to a receiver, and establishing synchronization between a transmitter and a receiver.
A burst signal having been modulated into a digital phase is designed to have a preamble at the head thereof for reproducing bit timing, to thereby establish synchronization.
Bit timing of quadrature phase shift keying (QPSK) is usually reproduced through the use of a preamble pattern in which signals existing on a diagonal line are repeatedly transmitted in such an arrangement of signal points as an arrangement illustrated in FIG. 3, which is a signal phase diagram, and has I-axis as an axis of abscissa and Q-axis as an axis of ordinate.
The above-mentioned reproduction of bit timing is controlled, for instance, by zero-cross detection in which timing at which a signal passes an origin is detected.
In zero-cross detection, there is used sampling data having a small amplitude around an origin. However, sampling data having a small amplitude is accompanied with a problem of being readily influenced by noises and non-linear strains to thereby generate errors.
In burst transmission system making use of digital phase modulation, it is necessary to rapidly carry out bit synchronization and demodulation such as reproduction of a carrier wave. To this end, a burst signal is provided at a head thereof with a preamble.
In order to enhance a transmission rate, it is preferable to shorten a preamble to thereby rapidly establish bit synchronization.
For instance, Japanese Unexamined Patent Publication No. 5-211532 has suggested a rapid bit synchronization system in which a xcfx80/2-shifted BPSK signal or a xcfx80/4-shifted QPSK signal is employed, and needs to have a zero-xcfx80/2 modulated preamble or a zero-3xcfx80/4 modulated preamble, respectively.
A signal obtained by detecting a xcfx80/2-shifted BPSK signal or a xcfx80/4-shifted QPSK signal in quasi-synchronization is digitally quantized into one bit signal by means of an analog-digital converter through the use of clock signals transmitted from an oscillator, and then, variation in phase is detected by a phase-variation detector.
A complex sine wave generator generates a complex sine wave having a frequency of N/2 in response to a clock signal transmitted from an oscillator. A multiplier multiplies the thus generated complex sine wave by the variation in phase detected by the phase-variation detector to thereby calculate a relation in phase between a frequency component of 1/2 bit and the complex sine wave. The result of calculation is averaged through a low-pass filter, and then, a reverse tangent of an output transmitted from the low-pass filter is calculated by a reverse tangent calculator.
The reverse tangent calculator transmits its output at a timing which is represented within xc2x1xcfx80 under a two-bit interval. In order to covert a bit timing of an output timing of the reverse tangent calculator into a bit timing represented within xc2x1xcfx80 under a one-bit interval, the reverse tangent is doubled by means of a doubling device, and a remainder is calculated when the thus doubled reverse tangent is divided by 2xcfx80.
An output transmitted from an analog-digital converter is sampled or interpolated by a sampler or an interpolator at a bit timing at which the doubling device generates an output.
Japanese Unexamined Patent Publication No. 5-260107 has suggested a perpendicular modulator for demodulating n-PSK wave signals, wherein n indicates phase modulation. The suggested perpendicular modulator interpolates sampled n-PSK wave signals when n-PSK wave signals are digitally sampled and perpendicularly detected.
The suggested perpendicular modulator is designed to include two analog-digital converters for sampling n-PSK wave signals at a constant interval to thereby reproduce base band signals. Then, the thus reproduced base band signals are interpolated by means of an interpolation circuit. A re-timing device carries out re-timing treatment to the thus interpolated base band signals in response to a bit timing signal. Then, a detector detects the thus re-timed base band signals to thereby reproduce data sequence. Then, a bit timing reproducer generates a bit timing signal, based on a timing of the thus reproduced data sequence.
Japanese Unexamined Patent Publication No. 6-284159 has suggested a digital demodulator including a clock synchronization circuit which extracts a phase component of received clocks, and control a phase of a timing clock.
In accordance with the suggested digital demodulator, a base band signal having been modulated under four-value digital modulation is sampled at a rate twice greater than a modulation rate to thereby convert the base band signal into digital data. Detection data detected by a delay detection circuit is judged by a judgement circuit with judgement timing clocks, and then, is transmitted to a limiter circuit having a function of interpolation.
The limiter circuit interpolates one or more of adjacent two sampling values of detected outputs, puts the thus interpolated value into a limiter, and transmits one-bit interpolated data to a digital band pass filter.
In response to transmission of an output from the digital band pass filter, a circuit for detecting an error in phase detects an error in phase in a timing clock. Then, the circuit for detecting an error in phase transmits a signal indicative of an error in phase to a circuit for reproducing a clock, in accordance with the result of comparison in phase between the thus detected error in phase and a current timing clock. Then, the circuit for reproducing a clock compensates for a phase of a timing clock.
Japanese Unexamined Patent Publication No. 7-50700 has suggested a circuit for reproducing a carrier wave for detecting a phase of preamble.
In the suggested circuit, first and second multipliers each multiplies an offset QPSK modulation wave by a reproduced carrier wave having a phase shifted by xcfx80/2 from a phase of the offset QPSK modulation wave. An output transmitted from the first multiplier is delayed by a half interval of symbol rate relative to an output transmitted from the second multiplier, by means of a delay circuit. Then, a phase comparator for reproducing a bit timing converts outputs transmitted from the delay circuit and the second multiplier into a signal having a phase including two phase-stable points.
Japanese Unexamined Patent Publication No. 7-212419 has suggested an apparatus for extracting a clock for detecting a phase of preamble.
In this apparatus, a relative phase of a carrier wave of a xcfx80/4-shifted QPSK is input into a relative phase detector. The relative phase detector includes first and second counters each of which counts signals having a frequency equal to a M times multiplied sum of a frequency of a carrier wave of a xcfx80/4-shifted QPSK signal transmitted from an oscillator and a shifted frequency.
The relative phase detector includes an amplitude limiter. The amplitude limiter slides an amplitude of the carrier wave to thereby transmit a rectangular wave as a carrier wave. A rise-up detecting circuit detects rise-up of the carrier wave, and resets the first counter. Then, a circuit for subtraction subtracts an output transmitted from the first counter from an output transmitted from the second counter to thereby transmit a relative phase of the carrier wave of the xcfx80/4-shifted QPSK signal.
Then, the subtraction circuit calculates a difference between the relative phase and a phase prior to the relative phase by a half symbol. When a phase difference detector detects that the thus calculated difference becomes equal to a predetermined value, a reference signal generator transmits a reference signal.
On the other hand, a demodulator may be designed to include a limiter amplifier for suppressing fluctuation in an input level to be introduced to the demodulator. The limiter amplifier keeps an output level transmitted from the demodulator constant regardless of an input level. As a result, it is no longer necessary to use a preamble for AGC, which ensures a shorter preamble.
However, the use of a limiter amplifier is accompanied with a problem that performances of the demodulator is much deteriorated due to non-linear strain which is caused by the limiter amplifier. Hence, the demodulator is necessary to be provided with a countermeasure against such non-linear strain
All of the above-mentioned conventional apparatuses or circuits are not provided with a countermeasure to avoid influences due to non-linear strain and/or an error caused by noises, and hence, are accompanied with a problem of deterioration of performances due to non-linear strain.
In view of the above-mentioned problem, it is an object of the present invention to provide a circuit for reproducing a bit timing and a method of doing the same both of which are hardly influenced by noises and errors caused by non-linear strain, and are capable of fabricating a semiconductor device in a smaller size to thereby reduce power consumption.
In one aspect of the present invention, there is provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter for converting an imaginary part signal of the complex modulation signal into an imaginary part digital signal, (c) a first detector for receiving the real part digital signal and the imaginary part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation signals in the symbol interval, (f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the second detector, and transmitting a second signal indicative of the timing gap, and (g) a signal converter for converting each of the real part digital signal and the imaginary part digital signal into a signal associated with the optimum sampling point, based on the second signal.
In accordance with the above-mentioned circuit, the first analog-digital converter converts a real part signal of a complex modulation signal, which has a base band frequency band and is obtained from a received modulation signal having been modulated into a digital phase, into a real part digital signal, and the second analog-digital converter converts an imaginary part signal of the complex modulation signal into an imaginary part digital signal. The thus obtained real part digital signal and imaginary part digital signal are input into the first detector.
The first detector having received the real part digital signal and the imaginary part digital signal detects a phase angle of the complex modulation signal on a complex plane, and then, transmits the first signal indicative of the phase angle, to both the delay circuit and the second detector. The delay circuit delays the first signal by a symbol interval, and then, transmits the delayed first signal to the second detector. The second detector makes subtraction between the first signal and an output signal transmitted from the delay circuit to thereby detect a difference in phase on the complex plane between the complex modulation signals in the symbol interval. A signal indicative of the thus detected difference in phase is transmitted to the third detector.
The third detector detects a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase detected by the second detector, and transmits the second signal indicative of the timing gap to the signal converter.
The signal converter converts each of the real part digital signal and the imaginary part digital signal into a signal associated with the optimum sampling point, based on the second signal.
The circuit in accordance with the invention is hardly influenced by noises and errors caused by non-linear strain, and makes it possible to fabricate a semiconductor device in a smaller size, reduce power consumption, and accomplish maintenance free.
It is preferable that the above-mentioned circuit further includes a clock oscillator transmitting fixed clock signals, in which case, the first analog-digital converter samples and quantizes the real part signal with the fixed clock signals to thereby convert the real part signal into the real part digital signal.
It is also preferable that the above-mentioned circuit further includes a clock oscillator transmitting fixed clock signals, in which case, the second analog-digital converter samples and quantizes the imaginary part signal with the fixed clock signals to thereby convert the imaginary part signal into the imaginary part digital signal.
For instance, the second detector may be comprised of a subtracter for making subtraction between the first signal and an output signal transmitted from the delay circuit.
There is further provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter for converting an imaginary part signal of the complex modulation signal into an imaginary part digital signal, (c) a first detector for receiving the real part digital signal and the imaginary part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation signals in the symbol interval, (f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the second detector, and transmitting a second signal indicative of the timing gap, (g) a first interpolating filter for converting the real part digital signal into a signal associated with an optimum sampling point, based on the second signal, and (h) a second interpolating filter for converting the imaginary part digital signal into a signal associated with an optimum sampling point, based on the second signal.
There is still further provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter for converting an imaginary part signal of the complex modulation signal into an imaginary part digital signal, (c) a first detector for receiving the real part digital signal and the imaginary part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation signals in the symbol interval, (f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the second detector, and transmitting a second signal indicative of the timing gap, (g) a clock oscillator for transmitting fixed clock signals, and (h) a programmable phase shifter for shifting a phase of the fixed clock signals, based on the second signal.
In another aspect of the present invention, there is provided a method of reproducing bit timing, including the steps of (a) converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) converting an imaginary part signal of the complex modulation signal into an imaginary part digital signal, (c) detecting a phase angle of the complex modulation signal on a complex plane, based on the real part digital signal and the imaginary part digital signal, and transmitting a first signal indicative of the thus detected phase angle, (d) delaying the first signal by a symbol interval, (e) detecting a difference in phase on the complex plane between the complex modulation signals in the symbol interval, (f) detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, and (g) converting each of the real part digital signal and the imaginary part digital signal into a signal associated with the optimum sampling point, based on the timing gap.
It is preferable that the real part signal is sampled and quantized with fixed clock signals to thereby be converted into the real part digital signal in the step (a).
It is also preferable that the imaginary part signal is sampled and quantized with fixed clock signals to thereby be converted into the imaginary part digital signal in step (b).
For instance, the difference in phase may be detected by making subtraction between the complex modulation signals in the symbol interval in the step (e).
There is further provided a method of reproducing bit timing, including the steps of (a) converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) converting an imaginary part signal of the complex modulation signal into an imaginary part digital signal, (c) detecting a phase angle of the complex modulation signal on a complex plane, based on the real part digital signal and the imaginary part digital signal, and transmitting a first signal indicative of the thus detected phase angle, (d) delaying the first signal by a symbol interval, (e) detecting a difference in phase on the complex plane between the complex modulation signals in the symbol interval, (f) detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, and (g) shifting a phase of fixed clock signals, based on the timing gap.
In the specification, BPSK is an acronym of xe2x80x9cBinary Phase Shift Keyingxe2x80x9d, QPSK is an acronym of xe2x80x9cQuadrature Phase Shift Keyingxe2x80x9d, MSK is an acronym of xe2x80x9cMinimum Shift Keyingxe2x80x9d, and GMSK is an acronym of xe2x80x9cGaussian filtered Minimum Phase Shift Keyingxe2x80x9d.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.